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high voltage, low noise, low distortion, unity - gain stable, high speed op am p data sheet ada4898 - 1 / ada4898 - 2 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no r e sponsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2008 - 2012 analog d evices, inc. all rights reserved. features ultralow noise 0.9 nv/hz 2.4 pa/hz 1.2 nv/hz at 10 hz ultralow distortion: ?93 dbc at 500 khz wide supply voltage range: 5 v to 16 v high speed ?3 db bandwidth: 65 mhz (g = +1) slew rate: 55 v/s unity gain stable low input offset voltage: 1 6 0 v maximum low input offset voltage drift: 1 v/c low input bias current: ?0.1 a low input bias current drift: 2 na/c supply current: 8 ma power - down feature for single 8 - lead package applications instrumentation active filters dac buffers sar adc d rivers optoelectronics connection diagram nc 1 ?in 2 +in 3 ?v s 4 pd 8 +v s 7 v out 6 nc 5 nc = no connect top view (not to scale) ada4898-1 07037-001 figure 1. single 8- lead ada4898 - 1 soic_n_ep (rd - 8- 1 ) 07037-050 v out1 1 ?in1 2 +in1 3 ?v s 4 +v s 8 v out2 7 ?in2 6 +in2 5 ada4898-2 top view (not to scale) figure 2 . dual 8 - lead ada4898 - 2 soic_n_ep (rd - 8- 2 ) general description the ada4898 is an ultralow nois e and distortion, unity gain stable, voltage feedback op amp that is ideal for use in 16 - bit and 18- bit systems with power supplies from 5 v to 16 v. the ada4898 features a linear, low noise input stage and internal co m pensation that achieves high slew r ates and low noise. with the wide su pply voltage range, low offset voltage, and wide bandwidth, the ada4898 is extremely versatile, and it features a cancellation circuit that reduces input bias current. the ada4898 is available in an 8 - lead soic package that features an exposed metal paddle to improve power dissipation and heat transfer to the negative supply plane. th is e pa d offers a significant thermal relief over traditional plastic packages. the ada4898 is rated to work over the extended industrial te mperature range of ? 40c to +105c. 07037-002 frequency (hz) voltage noise (nv/hz) current noise (pa/hz) 1 0.1 1 10 0.1 1 10 10 100 1k 10k 100k current voltage figure 3 . input voltage noise and current noise vs. frequency
ada4898- 1/ada4898 - 2 data sheet rev. d | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 connection diagram ....................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 15 v supply ................................................................................. 3 5 v supply ................................................................................... 4 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 maximum power dissipation ..................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 test circuits ..................................................................................... 13 theory of operation ...................................................................... 14 pd ( power - down ) pin for the ada4898 - 1 ............................ 14 0.1 hz to 10 hz noise ................................................................ 14 a pplications information .............................................................. 15 higher feedback resistor gain operation ............................. 15 recommended values for various gains ................................ 15 noise ............................................................................................ 16 circuit considerations .............................................................. 16 pcb layout ................................................................................. 16 power supply bypassing ............................................................ 16 grounding ................................................................................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 5 / 1 2 rev. c to rev. d changes to figure 2 caption ........................................................... 1 updated outline dimensions ....................................................... 17 changes to ordering guide .......................................................... 17 2 / 1 0 rev. b to rev. c added ada4898 - 2 ........................................................ through out changes to features .......................................................................... 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to figure 38, figure 40, figure 41 ................................. 14 changes to figure 46 ...................................................................... 15 changes to figure 47 ...................................................................... 16 changes to pcb layout section ................................................... 17 changes to ordering guide .......................................................... 20 6 /0 9 rev. a to rev. b changes to general description section ...................................... 1 changes to specifications section .................................................. 3 changes to figure 29 and figure 31 ............................................. 11 added figure 32 ............................................................................. 12 added figure 41 ............................................................................. 13 changes to pd (power - down) pin section ................................ 14 added table 6 ................................................................................. 14 changes to figure 45 ...................................................................... 15 8/08 rev. 0 to rev. a changes to general description section ....................................... 1 changes to table 5 ............................................................................. 6 changes to figure 17 ......................................................................... 9 changes to figure 28 ...................................................................... 10 changes to figure 29 and figure 32 ............................................ 11 added 0.1 hz to 10 hz noise section .......................................... 1 4 added figure 42 and figure 43; renumbered sequentially ..... 1 4 changes to grounding section ..................................................... 1 6 updated outline dimensions ....................................................... 1 7 5/08 revision 0: initial release
data sheet ada4898- 1/ada4898 - 2 rev. d | page 3 of 20 specifications 15 v supply t a = 25c, g = +1, r f = 0 ?, r g open, r l = 1 k? to gnd (for g > 1, r f = 100 ?), unless otherwise noted. table 1 . parameter conditions min typ max unit dynamic performance ?3 db bandwidth v out = 100 mv p -p 65 mhz v out = 2 v p -p 14 mhz band width for 0.1 db flatness g = +2, v out = 2 v p -p 3.3 mhz slew rate v out = 5 v step 55 v/s settling time to 0.1% v out = 5 v step 85 ns noise/distortion performance harmonic distortion sfdr f = 100 khz, v out = 2 v p -p ?116 dbc f = 500 khz, v out = 2 v p -p ?93 dbc f = 1 mhz, v out = 2 v p -p ?79 dbc input voltage noise f = 1 khz 0.9 nv/hz input current noise f = 1 khz 2.4 pa/hz dc performance input offset voltage r f = 1 k?, see figure 43 2 0 1 2 5 v input offset voltage drift r f = 1 k?, see figure 43 1 v/c input bias current r f = 1 k?, see figure 43 ?0.1 ?0.4 a input bias offset current r f = 1 k?, see figure 43 0.03 0.3 a input bias current drift r f = 1 k?, see figure 43 2 na/c open - loop gain v out = 5 v 99 103 db input characteristics input resistance differential mode 5 k? common mode 30 m? input capacitance differential mode 3.2 pf common mode 2. 5 pf input common - mode voltage range see figure 43 11 v common - mode rejection ratio v cm = 2 v ?103 ?126 db pd ( power - down ) pin (ada4898 - 1) pd input voltages chip powered down ?14 v chip enabled ?13 v pd turn on time v out = 100 mv p -p 100 ns pd turn off time v out = 100 mv p -p 20 s input leakage current pd = +v s 0.1 a pd = ?v s ?0.2 a output characteristics output voltage swing r l // (r f + r g ) = 500 ? , s ee figure 43 ?11. 0 to +11 .8 ?11.7 to +12. 1 v r l // (r f + r g ) = 1 k? , s ee figure 43 ?1 2 . 5 to +12. 5 ?1 2 . 8 to +12. 7 v linear output current f = 1 00 khz, sfdr = ?70 dbc, r l = 150 ? 40 ma short - circuit current sinking/sourcing 150 ma off isolation f = 1 mhz, pd = ? v s 80 db power suppl y operating range 4.5 16.5 v quiescent current per amplifier pd = +v s 7.9 8.7 ma pd = ?v s 0.1 0.3 ma positive power supply rejection ratio +v s = 15 v to 17 v, ?v s = ?15 v ?98 ?107 db negative power supp ly rejection ratio +v s = 15 v, ?v s = ?15 v to ?17 v ?100 ?114 db
ada4898- 1/ada4898 - 2 data sheet rev. d | page 4 of 20 5 v supply t a = 25c, g = +1, r f = 0 ?, r g open, r l = 1 k? to gnd (for g > 1, r f = 100 ?), unless otherwise noted. table 2 . parameter conditions min typ max unit dynamic performance ?3 db bandwidth v out = 100 mv p -p 57 mhz v out = 2 v p -p 12 mhz bandwidth for 0.1 db flatness g = +2, v out = 2 v p -p 3 mhz slew rate v out = 2 v step 50 v/s settling time to 0.1% v out = 2 v step 90 ns noise/distor tion performance harmonic distortion sfdr f = 1 00 khz, v out = 2 v p -p ? 110 dbc f = 500 khz, v out = 2 v p - p ? 95 dbc f = 1 mhz, v out = 2 v p -p ?78 dbc input voltage noise f = 1 khz 0.9 nv/hz input current noise f = 1 khz 2.4 pa/hz d c performance input offset voltage r f = 1 k?, see figure 43 30 1 6 0 v input offset voltage drift r f = 1 k?, see figure 43 1 v/c input bias current r f = 1 k?, see figure 43 ?0.1 ?0. 5 a input bias offset current r f = 1 k?, see figure 43 0.05 0.3 a input bias current drift r f = 1 k?, see figure 43 2 na/c open - loop gain v out = 1 v 87 94 db input characteristics input resistance differential mode 5 k? common mode 30 m? input capacitance differential mode 3.2 pf common mode 2. 5 pf input common - mode voltage range see figure 43 ?3 to +2.5 v common - mode rejection ratio v cm = 1 v p -p ?102 ?120 db pd (p ower - down ) pin (ada4898 - 1) pd input voltages chip powered down ?4 v chip enabled ?3 v pd turn on time v out = 100 mv p -p 100 ns pd turn off time v out = 100 mv p -p 20 s input leakage current pd = +v s 0.1 a pd = ?v s ?2 a output characteristics output voltage swing r l // (r f + r g ) = 500 ? , s ee figure 43 3.1 3. 2 v r l // (r f + r g ) = 1 k? , s ee figure 43 3. 3 3. 4 v linear output current f = 1 00 khz, sfdr = ?70 dbc, r l = 150 ? 8 ma short - circuit current sinking/sourcing 150 ma off isolation f = 1 mhz, pd = ?v s 80 db power supply operating range 4.5 16.5 v quiescent current per amplifier pd = +v s 7. 5 8.4 ma pd = ?v s 0.1 0.2 ma positive power supply rejection ratio +v s = 5 v to 7 v, ?v s = ?5 v ?95 ?100 db negative power supply rejection ratio +v s = 5 v, ?v s = ?5 v to ?7 v ?97 ?104 db
data sheet ada4898- 1/ada4898 - 2 rev. d | page 5 of 20 absolute maximum rat ings table 3 . parameter rating supply voltage 36 v power dissipation see figure 4 differential mode input voltage 1.5 v common - mode input voltage 11.4 v storage temperature range ?65c to +150c operating temperature range ?40c to +105c lead temperature (soldering, 10 sec) 300c junction temperature 150 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra t ing only; functional operation of the device at these or any other conditions above those indicated in the operational section of th is specification is not implied. exposure to abs o lute maximum rating conditions for extended periods may a f fect device reliability. thermal resistance ja is specifie d for the worst - case conditions; that is, ja is spec i fied for a device soldered in the circuit board with its exposed paddle soldered to a pad on the pcb surface that is thermally connected to a copper plane, with zero airflow. table 4 . package type ja jc unit single 8 - lead soic_n_ ep on a 4 - layer board 47 29 c/w dual 8 - lead soic_n_ ep on a 4 - layer board 42 29 c/w maximum power dissip ation the maximum safe power dissipation in the ada4898 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ada4898. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the pac kage (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the output load drive. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. for each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. rms voltages and currents must be used in these calculations. a irflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . the exposed paddle on the underside of the package m ust be soldered to a pad on the pcb surface that is thermally connected to a copper plane to achieve the specified ja . figure 4 shows the maximum power dissipation vs. the ambient temperature for the single and dual 8 - lead soi c_ n_ ep on a jedec standard 4 - layer board, with its underside paddle soldered to a pad that is thermally connected to a pcb plane. ja values are approximations. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 5.0 4.5 07037-003 ambient temperature (c) maximum power dissipation (w) 0 20 40 60 80 100 10 30 50 70 90 ?40 ?20 ?30 ?10 ada4898-2 ada4898-1 figure 4 . maximum power dissipation vs. ambient temperature esd caut ion
ada4898- 1/ada4898 - 2 data sheet rev. d | page 6 of 20 pin configuration s and function descrip tions 07037-046 nc 1 ?in 2 +in 3 ?v s 4 pd 8 +v s 7 v out 6 nc 5 ada4898-1 top view (not to scale) notes 1. exposed pad can be connected to the negative supply (?v s ) or left floating. figure 5. single 8 - lead soic_n_ep pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 nc no connect . 2 ?in invert ing input . 3 +in noninverting input . 4 ?v s negative supply . 5 nc no connect . 6 v out output . 7 +v s positive supply . 8 pd power down not . ep e xposed p ad . can be connected to the negative supply (?v s ) or can be left floating . 07037-051 v out1 1 ?in1 2 +in1 3 ?v s 4 +v s 8 v out2 7 ?in2 6 +in2 5 ada4898-2 top view (not to scale) notes 1. exposed pad can be connected to the negative supply (?v s ) or left floating. figu re 6. dual 8 - lead soic_n_ep pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 v out1 output 1 . 2 ?in 1 inverting input 1 . 3 +in 1 noninverting input 1 . 4 ?v s negative supp ly. 5 +in2 noninverting input 2 . 6 ?in2 inverting input 2 . 7 v out 2 output 2. 8 +v s positive supply. ep exposed pad. can be connected to the negative supply (?v s ) or can be left floating .
data sheet ada4898- 1/ada4898 - 2 rev. d | page 7 of 20 typical performance characteristics ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 1 10 100 07037-004 frequency (mhz) normalized closed-loop gain (db) r l = 1k? v out = 100mv p-p v s = 15v g = +1 r f = 0? g = +1 r f = 100? g = +2 r f = 100? g = +5 r f = 100? figure 7 . small signal frequency response for various gains ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 1 10 100 07037-005 frequency (mhz) closed-loop gain (db) r l = 1k? r l = 100? r l = 200? g = +1 v out = 100mv p-p v s = 15v figure 8 . small signal frequency response for various loads ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 07037-006 frequency (mhz) closed-loop gain (db) t a = +25c g = +1 r l = 1k? v out = 100mv p-p v s = 15v t a = +105c t a = +85c t a = ?40c t a = 0c figure 9 . small signal frequency response for various temperatures ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 1 10 100 07037-007 frequency (mhz) normalized closed-loop gain (db) r l = 1k? v out = 2v p-p v s = 15v g = +1 r f = 0? g = +1 r f = 100? g = +5 r f = 100? g = +2 r f = 100? figure 10 . large signal frequency response for various gains ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 1 10 100 07037-008 frequency (mhz) closed-loop gain (db) r l = 1k? r l = 100? g = +1 v out = 2v p-p v s = 15v r l = 200? figure 11 . large signal frequency response for various loads ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 07037-009 frequency (mhz) closed-loop gain (db) g = +1 r l = 1k? v out = 2v p-p v s = 15v t a = ?40c t a = +105c t a = +25c t a = 0c t a = +85c figure 12 . large signal frequency response for v arious temperatures
ada4898- 1/ada4898 - 2 data sheet rev. d | page 8 of 20 ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 07037-010 frequency (mhz) closed-loop gain (db) g = +1 r l = 1k? v out = 100mv p-p v s = 15v v s = 5v figure 13 . small signal frequency response for various supply voltages ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 1 10 100 07037-011 frequency (mhz) closed-loop gain (db) g = +1 r l = 1k? v out = 100mv p-p v s = 15v c l = 33pf c l = 15pf c l = 5pf c l = 0pf figure 14 . small signal frequency response for various capacitive loads 0.1 1 10 1 10 100 1k 10k 100k 07037-012 frequency (hz) voltage noise (nv/hz) figure 15 . voltage noise vs. frequency ?12 ?11 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 1 10 100 07037-013 frequency (mhz) closed-loop gain (db) v s = 15v g = +1 r l = 1k? v out = 2v p-p v s = 5v figure 16 . large signal frequency response for various supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 100k 1m 10m 07037-014 frequency (hz) normalized gain (db) g = +2 r l = 1k? v s = 15v v out = 2v p-p v out = 0.1v p-p figure 17 . 0.1 db flatness for various output voltages 07037-035 frequency (hz) input current noise (pa/ hz) 1 1 10 100 10 100 1k 10k 100k figure 18 . input current noise vs. frequency
data sheet ada4898- 1/ada4898 - 2 rev. d | page 9 of 20 ?20 ?10 0 10 20 30 40 50 60 70 80 110 90 100 07037-016 frequency (hz) open-loop gain (db) 100k 1m 1g 10m 100m phase gain ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 ?180 ?190 ?200 open-loop phase (degrees) v out = 5v v s = 15v figure 19 . open - loop gain and phase vs. frequency 07037-017 frequency (hz) distortion (dbc) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100k 1m 10m g = +1, hd2 g = +1, hd3 g = +2, hd3, r f = 250? g = +2, hd2, r f = 250? r l = 1k? v s = 15v v out = 2v p-p figure 20 . harmonic distortion vs. frequency and gain 07037-018 frequency (hz) distortion (dbc) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100k 1m 10m r l = 1k?, hd3 r l = 100?, hd3 g = +1 v s = 15v v out = 2v p-p r l = 1k?, hd2 r l = 100?, hd2 figure 21 . harmonic d istortion vs. frequency and loads 1 07073-019 output voltage (v p-p) distortion (dbc) ?135 ?125 ?120 ?130 ?115 ?110 ?105 ?100 ?95 2 3 4 5 6 hd2 hd3 f = 100khz g = +1 r l = 1k? v s = 15v figure 22 . harmonic distortion vs. output amplitude 07037-020 frequency (hz) distortion (dbc) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100k 1m 10m r l = 1k?, hd3 r l = 100?, hd3 r l = 100?, hd2 g = +1 v s = 5v v out = 2v p-p r l = 1k?, hd2 figure 23 . harmonic distortion vs. frequency and loads ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 c l = 0pf c l = 5pf c l = 15pf c l = 33pf 07037-021 time (20ns/div) output voltage (v) v out = 100mv p-p g = +1 r l = 1k? v s = 15v figure 24 . small signal tr ansient response for various capacitive loads
ada4898-1/ada4898-2 data sheet rev. d | page 10 of 20 g = +1 g = +2 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 07037-022 time (20ns/div) output voltage (v) v out = 100mv p-p r l =1k ? v s = 15v figure 25. small signal transient response for various gains ?0.5 0 0.5 1.0 1.5 2.0 2.5 v s = 15v v s = 5v 07037-023 time (100ns/div) output voltage (v) v out = 2v p-p g = +1 r l = 100 ? figure 26. large signal transient response for various supply voltages, r l = 100 input 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 07037-026 time (10ns/div) settling time (%) g = +1 r l = 1k ? v out = 5v p-p v s = 15v ? t = 85ns output figure 27. settling time ?0.5 0 0.5 1.0 1.5 2.0 2.5 07037-025 time (100ns/div) output voltage (v) v out = 2v p-p g = +1 r l = 1k ? v s = 15v v s = 5v figure 28. large signal transient response for various supply voltages, r l = 1 k ?0.5 0 0.5 1.0 1.5 2.0 2.5 g = +1 07037-024 time (100ns/div) output voltage (v) v out = 2v p-p r l = 1k ? v s = 15v g = +2 figure 29. large signal transient response for various gains 0.1 10k 1k 100 10 1 07037-028 frequency (hz) output impedance ( ? ) 100k 1m 100m 10m pd high g = +1 r f = 0 ? v s = 15v pd low figure 30. output im pedance vs. frequency
data sheet ada4898-1/ada4898-2 rev. d | page 11 of 20 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 07037-029 frequency (hz) cmrr (db) 100 10m 1k 100k 1m 10k g = +1 r f = 0 ? r l = 100 ? v s = 15v ? v cm = 1v p-p ? v cm = 100mv p-p figure 31. common-mode rejection ratio (cmrr) vs. frequency ?75 ?65 ?55 ? 45 100k 1m 10m 100m v out = 0.1v p-p 07037-031 frequency (hz) pd isolation (db) g = +1 r l = 1k ? v s = 15v v out = 2v p-p figure 32. pd input to output isolation vs. frequency ?120 ?100 ?80 ?60 ?40 ?20 0 07037-030 frequency (hz) psrr (db) 100 1k 10k 100k 1m 10m g = +1 r f = 0 ? r l = 100 ? v s = 15v v out = 2v p-p +psrr ?psrr figure 33. power supply rejectio n ratio (psrr) vs. frequency 07037-100 15 12 9 6 3 0 5 4 3 2 1 0 50 100 1000 4000 output voltage swing (v), v s = 15 v output voltage swing (v), v s = 5v load resistance ( ? ) positive swing, v s = +15v negative swing, v s = ?15v positive swing, v s = +5v negative swing, v s = ?5v figure 34 output swing vs. load, g = +2, load = r l // (r f + r g ) ?110 ? 40 ?50 ?60 ?70 ?80 ?90 ?100 07037-101 frequency (mhz) crosstalk (db) 1 10 100 g = +1 r l = 1k ? v out = 2v p-p +in1 to v out2 , v s = 5v +in1 to v out2 , v s = 15v +in2 to v out1 , v s = 5v +in2 to v out1 , v s = 15v figure 35. crosstalk vs. frequency
ada4898- 1/ada4898 - 2 data sheet rev. d | page 12 of 20 1000 800 600 400 200 0 07037- 032 input bias current ( a) count ?0.15 ?0.20 ?0.25 ?0.10 0 ?0.05 n = 6180 mean: ?0.13 sd: 0.02 v s = 15v figure 36 . input bias current distribution 1000 800 600 400 200 0 07037- 033 input offset voltage ( v) count 0 ?30 ?60 30 120 90 60 n = 6180 mean: 27 sd: 20 v s = 15v figure 37 . input offset voltage distribution, v s = 15 v
data sheet ada4898- 1/ada4898 - 2 rev. d | page 13 of 20 test circuits in v out 10f +v s ?v s 49.9? r l 0.1f 0.1f + 10f 07037-052 + figure 38 . typical noninverting load configu ration v out 0.1f 49.9? +v s ?v s r l 10f + ac 07037-053 figure 39 . positive power supply rejection in v out 10f +v s ?v s 1k? 1k? 1k? 1k? 53.6? r l + 10f + 07037-054 0.1f 0.1f figure 40 . common - mode rejection in v out 10f +v s ?v s r g r f 49.9? r l c l + 10f 07037-055 + 0.1f 0.1f figure 41 . typical capacitive load configuration 0.1f v out +v s ?v s r l 10f + ac 49.9? 07037-056 figure 42 . negative power supply rejection 07037-139 +v s ?v s +i b ?i b 200? 1k? v control r in = 20? r f = 1k? in-amp v out figure 43 . dc test circuit
ada4898-1/ada4898-2 data sheet rev. d | page 14 of 20 theory of operation the ada4898 is a voltage feedback op amp that combines unity gain stability with 0.9 nv/hz input noise. it employs a highly linear input stage that can maintain greater than ?90 dbc (at 2 v p-p) distortion out to 600 khz while in a unity-gain configuration. this rare combination of unity gain stability, low input-referred noise, and extremely low distortion is the result of analog devices, inc., proprietary op amp architecture and high voltage bipolar processing technology. the simplified ada4898 topology, shown in figure 44, is a single gain stage with a unity gain output buffer. it has over 100 db of open-loop gain and maintains precision specifications, such as cmrr, psrr, and offset, to levels that are normally associated with topologies having two or more gain stages. buffer g m c c r1 r l v out 07037-041 figure 44. topology pd (power-down) pin for the ada4898-1 the pd pin saves power by decreasing the quiescent power dissipated in the device. it is very useful when power is an issue and the device does not need to be turned on at all times. the response of the device is rapid when going from power-down mode to full power operation mode. note that pd does not put the output in a high-z state, which means that the ada4898 is not recommended for use as a multiplexer. leaving the pd pin floating keeps the amplifier in full power operation mode. table 7. power-down voltage control pd pin 15 v 10 v 5 v power-down mode ?14 v ?9 v ?4 v 0.1 hz to 10 hz noise figure 45 shows the 0.1 hz to 10 hz voltage and current noise of the ada4898. the peak-to-peak noise voltage is below 0.5 v. figure 46 shows the circuit used to measure the low frequency noise. it uses a band-pass filter of approximately 0.1 hz and 10 hz and a high gain stage feeding into an instrumentation amplifier. 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 02 468101214161820 time (s) output voltage (v) 07037-047 figure 45. 0.1 hz to 10 hz noise dut ada4898-1 +in ?in 1f 10nf 10nf 50? 50? +in ?in ad743 ?v s = ?9v +v s = +9v 1f 15.8k ? 13k ? 13? momentary 1k? 806k ? 806k ? 7805 7905 +v s = +9v (battery) ?v s = ?9v (battery) +v r = +5v ?v r = ?5v +v r = +5v ?v r = ?5v ad620 r g ?in +in ?v s r g +v s output ref r = 5.36k ? , gain approx. 10 ? 10nf 1 2 4 3 8 7 5 6 10nf +v s = +9v ?v s = ?9v floating shield coax tek tds 754a scope in faraday cage 07037-048 out figure 46. low frequency noise circuit
data sheet ada4898- 1/ada4898 - 2 rev. d | page 15 of 20 applications informa tion higher feedback resis tor gain operation the ada4898 schematic for the noninverting gain configur a tion shown in figure 47 i s nearly a textbook example . the only exception is the feedback capacitor in parallel with the feedback re sistor, r f , but this capacitor is recommended only when using a large r f value (>300 ?). figure 48 shows the difference between using a 100 ? resistor and a 1 k? feedback resistor. due to the high input capacitance in the ada4898 when using a higher feedback resistor, more peaking appears in the c losed - loop gain. using the lower feedback resistor resolves this issue; however, when running at higher supplies (15 v) with an r f of 100 ?, the system draws a lot of extra current into the feedback network. to avoid this problem, a higher feedback resist or can be used with a feedback capacitor in parallel. figure 48 s hows the effect of placing a feedback capacitor in parallel with a larger r f . in this gain - of - 2 configuration, r f = r g = 1 k? and c f = 2.7 pf. when using c f , t he peaking drops from 6 db to less than 2 db. 07037-043 v in v out 10f +v s ?v s r t r l + 10f + c f r f r f 0.1f 0.1f figure 47 . noninverting gain schematic ?15 ?12 ?9 ?6 ?3 0 3 6 9 12 07037-044 frequency (hz) closed-loop gain (db) 100k 10m 1m 100m r f = 1k?, c f = 2.7pf r f = 1k? r f = 100? g = +2 r l = 1k? v s = 15v figure 48 . small signal frequency response for various feedback impedances recommended values f or various gains table 8 provides a useful reference for determining various gains and associated performance. r f is set to 100 ? for gains greater than 1. a low feedback r f resistor value reduces peaking and minimizes the contribution to the overall noise performance of the amplifier. table 8 . gains and recommended resistor values associa ted w ith them (conditions: v s = 5 v, t a = 25c, r l = 1 k?, r t = 49.9 ?) gain r f (?) r g (?) ?3 db ss bw (mhz), v out = 100 mv p - p slew rate (v/s), v out = 2 v step ada4898 voltage noise (nv/hz), rto total system noise (nv/hz), rto +1 0 n / a 65 55 0.9 1. 29 +2 100 100 30 50 1.8 3.16 +5 100 24.9 9 45 4.5 7.07
ada4898- 1/ada4898 - 2 data sheet rev. d | page 16 of 20 noise to analyze the noise performance of an amplifier circuit, identify the noise sources, and then determine if each source has a si g nificant contribution to the overall noise performance of the amplifier. to simplify the noise calculations, noise spectral densities were used rather than actual voltages to leave bandwidth out of the expressions . n oise spectral density, which is generally expressed in nv/ hz, is equivalent to the noise in a 1 hz b andwidth . the noise model shown in figure 49 has six individual noise sources: the johnson noise of the three resistors, the op amp voltage noise , and the current noise in each input of the amplifier. each noise source has i ts own contribution to the noise at the output. noise is generally specified as referr ing to input (rti), but it is often simpler to calculate the noise referred to the output (rto) and then divide by the noise gain to obtain the rti noise. gain from b to output = ? r2 r1 gain from a to output = noise gain = ng = 1 + r2 r1 i n? v n v n, r1 v n, r3 r1 r2 i n+ r3 4ktr2 4ktr1 4ktr3 v n, r2 b a v n 2 + 4ktr3 + 4ktr1 r2 2 r1 + r2 i n+ 2 r3 2 + i n? 2 r1 r2 2 + 4ktr2 r1 2 r1 + r2 r1 + r2 rti noise = rto noise = ng rti noise v out + 07037-045 figure 49 . op amp noise analysis model all resistors have a johnson noise that is calculated by ) (4 kbtr where: k is boltzmanns c onstant (1.38 10 ?23 j/k). b is the bandwidth in hertz. t is the absolute temperature in kelvin. r is the resistance in ohms. a simple relationship that is easy to remember is that a 50 ? resistor generates a johnson noise of 1 nv/ hz at 25c. in applications where noise sensitivity is critical, care must be taken not to introduce other significant noise sources to the amplifier. each resistor is a noise source. attention to the following areas is critical to maintain low noise performance: d e sign, layout, and component selection. a summary of noise performance for the amplifier and associated resis tors is shown in table 8 . circuit consideratio ns careful and deliberate attention to detail when laying out the ada4898 board yields optimal performance. power supply bypassing, parasitic capacitance, and component selection a ll contribute to the overall performance of the amplifier. pcb layout because the ada4898 has a small signal bandwidth of 65 mhz, i t is essential that high frequency board layout techniques be employed. all ground and power planes under the pins of the ad a4898 should be cleared of copper to prevent the formation of parasitic capacitance between the input pins to ground and the output pins to ground. a single mounting pad on a soic footprint can add as much as 0.2 pf of capaci t ance to ground if the ground plane is not cleared from under the mounting pads. power supply bypassi ng power supply bypassing for the ada4898 has been optimized for frequency response and distortion performance. figure 47 shows the recommended values and location of the bypass capacitors. power supply bypassing is critical for stability, frequency response, distortion, and psr performance. the 0.1 f capacitors shown in figure 47 should be as close to the supply pins of the a da4898 as possible. the 10 f electrolytic capac i tors should be adjacent to , but not necessar il y close to , the 0.1 f capacitors. the capacitor between the two supplies helps improve psr and distortion performance. in some cases, additional paralleled cap acitors can help improve frequency and transient response. grounding ground and power planes should be used where possible. ground and power planes reduce the resistance and inductance of the power planes and ground returns. the returns for the input and output terminations, bypass capacitors, and r g should all be kept as close to the ada4898 as possible. the output load ground and the bypass capacitor grounds should be returned to the same point on the ground plane to minimize parasitic trace inductance, ringing, and overshoot and to improve distortion performance. the ada4898 package features an exposed paddle. for optimum electrical and thermal performance, solder this paddle to a nega - tive supply plane.
data sheet ada4898-1/ada4898-2 rev. d | page 17 of 20 outline dimensions compliant to jedec standards ms-012-a a controlling dimensions are in millimeter; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.050) 0.40 (0.016) 0.50 (0.020) 0.25 (0.010) 45 8 0 1.75 (0.069) 1.35 (0.053) 1.65 (0.065) 1.25 (0.049) seating plane 85 4 1 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 1.27 (0.05) bsc 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) 0.51 (0.020) 0.31 (0.012) coplanarity 0.10 top view 2.29 (0.090) bottom view (pins up) 2.29 (0.090) 0.10 (0.004) max for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 07-28-2008-a figure 50. 8-lead standard small outlin e package with exposed pad [soic_n_ep] (rd-8-1) dimensions shown in millimeters and (inches) compliant to jedec standards ms-012-a a controlling dimensions are in millimeter; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.050) 0.40 (0.016) 0.50 (0.020) 0.25 (0.010) 45 8 0 1.75 (0.069) 1.35 (0.053) 1.65 (0.065) 1.25 (0.049) seating plane 85 4 1 5.00 (0.197) 4.90 (0.193) 4.80 (0.189) 4.00 (0.157) 3.90 (0.154) 3.80 (0.150) 1.27 (0.05) bsc 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) 0.51 (0.020) 0.31 (0.012) coplanarity 0.10 top view 3.098 (0.122) bottom view (pins up) 2.41 (0.095) 0.10 (0.004) max for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 07-28-2008-a figure 51. 8-lead standard small outlin e package with exposed pad [soic_n_ep] (rd-8-2) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package descriptio n package option ordering quantity ada4898-1yrdz ?40c to +105c 8-lead soic_n_ep rd-8-1 98 ADA4898-1YRDZ-R7 ?40c to +105c 8-lead soic_n_ep rd-8-1 1,000 ada4898-1yrdz-rl ?40c to +105c 8-lead soic_n_ep rd-8-1 2,500 ada4898-2yrdz ?40c to +105c 8-lead soic_n_ep rd-8-2 98 ada4898-2yrdz-r7 ?40c to +105c 8-lead soic_n_ep rd-8-2 1,000 ada4898-2yrdz-rl ?40c to +105c 8-lead soic_n_ep rd-8-2 2,500 ada4898-1yrd-ebz evaluation board ada4898-2yrd-ebz evaluation board 1 z = rohs compliant part.
ada4898- 1/ada4898 - 2 data sheet rev. d | page 18 of 20 notes
data sheet ada4898- 1/ada4898 - 2 rev. d | page 19 of 20 notes
ada4898- 1/ada4898 - 2 data sheet rev. d | page 20 of 20 notes ? 2008 - 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owne rs. d07037 - 0- 5/12(d)

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